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| Ordering number : ENA0693 Bi-CMOS LSI LV5609V Overview For CCD Vertical Clock Driver The LV5609V is vertical clock driver for CCD. Functions * Ternary output x2ch * Binary output x2ch * SHT output x1ch * Output ON resistance : 30 typ Specifications Absolute Maximum Ratings at Ta = 25C, VSS = VM = 0V Parameter Maximum supply voltage Symbol VDD max VH max VL max VH-VL max Allowable power dissipation Operating temperature Storage temperature * : Specified substrate : Pd max Topr Tstg 114.3x76.1x1.6mm3, glass epoxy board with specified substrate * Conditions Ratings 6 20 -10 24 0.67 -20 to +80 -40 to +125 Unit V V V V W C C Allowable Operating Ratings at Ta = 25C, VSS = VM = 0V Parameter Supply voltage Symbol VDD VH VL VH-VL CMOS input High voltage CMOS input Low voltage VINH VINL 0.8VDD -0.1 -8.5 Conditions min 2.0 Ratings typ 3.3 15 -7.5 max 5.5 17 -4 23.5 VDD 0.4 V V V V V V Unit Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before using any SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein. 32207 MS PC 20061109-S00003 No.A0693-1/8 LV5609V Electrical Characteristics at Ta = 25C, VDD = 3.3V, VSS = 0V, VH = 15V, VL = -7.5V, VM = 0V, Unless otherwise specified Parameter Static current drain Symbol IDD IH IL Dynamic current drain IDD IH IL Output ON resistance RL RM RH RSHT Propagation delay time TPLM TPMH TPLH TPML TPHM TPHL Rise time TTLM VDD pin VH pin VL pin VDD pin See *1 and *2. VH pin See *1 and *2. VL pin See *1 and *2. IO = +10mA IO = 10mA IO = -10mA IO = -10mA No load No load No load No load No load No load VL VM V1, V3 See *1. VL VM V2, V4 See *1. TTMH TTLH Fall time TTML VM VL V1, V3 See *1. VL VH SHT See *1. VM VL V1, V3 See *1. VM VL V2, V4 See *1. TTHM TTHL *1 : Refer to the CCD equivalent load shown below. *2 : Refer to the timing waveform on Page 7. VH VM V1, V3 See *1. VH VL SHT See *1. 2.4 3 20 30 30 30 Conditions min Ratings typ max 1 10 1 1 4.5 5 30 45 40 40 200 200 200 200 200 200 800 800 800 200 800 800 800 200 A A A mA mA mA ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit 2000pF 2000pF 1000pF V1 (Ternary) V4 (Ternary) 3000pF 3000pF SHT 1000pF V2 (Binary) V3 (Binary) 1600pF 2000pF 2000pF No.A0693-2/8 LV5609V Package Dimensions unit : mm (typ) 3179C 1.0 Pd max - Ta Specified circuit board : 114.3x76.1x1.6mm3 glass epoxy board 6.5 20 11 Allowable power dissipation, Pd max - W 0.8 0.67 0.6 4.4 6.4 0.5 0.4 0.30 0.2 1 0.65 (0.33) 10 0.22 1.5max 0.15 (1.3) 0 - 20 0 20 40 60 80 100 Ambient temperature, Ta - C 0.1 SANYO : SSOP20(225mil) No.A0693-3/8 LV5609V Pin Assignment SSOP20 V3 V2 V1 VM NC VH XV1 XSG1 XV2 1 2 3 4 5 20 V4 19 SHT 18 NC 17 VL 16 VSS LV5609V 6 7 8 9 15 VDD 14 XSHT 13 NC 12 XV4 11 XSG3 XV3 10 Top view Pin Function Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name V3 V2 V1 VM NC VH XV1 XSG1 XV2 XV3 XSG3 XV4 NC1 XSHT VDD VSS VL NC SHT V4 Level shift output (binary VH, VL) Level shift output (ternary VM, VL) SHT pulse input Power supply (3.3V system) for input buffer GND for input buffer LO power supply (-7.5V system) for output Hi power supply (15V system) for output V1 transfer pulse input V1 read pulse input V2 transfer pulse input V3 transfer pulse input V3 read pulse input V4 transfer pulse input Level shift output (ternary VH, VM, VL) Level shift output (binary VM, VL) Level shift output (ternary VH, VM, VL) GND for output Mode No.A0693-4/8 LV5609V Block Diagram VDD 0.1F 20 Input Buffer Level Shift & Output Buffer 9 VH 1F XV1 12 30 XSG1 13 XV2 14 30 5 V2 6 V1 7 VM XV3 15 30 XSG3 16 XV4 17 30 3 V4 4 V3 XSHT 18 30 2 SHT VSS 21 1 VL 1F Logical Function Table Input XV1 XV3 L L H H X X X X XSG1 XSG3 L H L H X X X X XV2 XV4 X X X X L H X X XSHT X X X X X X L H V1 V3 VH VM VL VL X X X X Output V2 V4 X X X X VM VL X X SHT X X X X X X VH VL No.A0693-5/8 LV5609V Timing Chart VDD XV1 to XV4 VSS VDD 50% VSS TPMH TTMH TTLM TPLM VM VL 90% 10% TTLM TPLM V2 V4 VM VL 90% 10% TPML TTML 10% 90% TPML TTML 50% 50% XSG1 XSG3 TPHM TTHM VH V1 V3 VDD XSHT VSS TTLH TPLH VH SHT VL 90% 10% TPHL TTHL 50% 50% No.A0693-6/8 LV5609V CCD Equivalent Load Measurement Timing Waveform 63.5s 2s XV1 127s XV2 XV3 XV4 XSG1 2.5s XSG3 2s XSHT 63.5s 2.5s 16.7ms Enlarged View of overlapped portion XV1 XV2 XV3 XV4 0s 0.7s 1.4s 2.1s 2.8s 3.5s 4.2s 4.9s No.A0693-7/8 LV5609V Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor products (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Semiconductor Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of March, 2007. Specifications and information herein are subject to change without notice. PS No.A0693-8/8 |
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